Field
The disclosed technology relates to methods of manufacturing semiconductor devices, and particularly to methods of manufacturing stacked nanowires MOS transistors.
Description of the Related Technology
Higher density semiconductor manufacturing, with corresponding decreases to sub-20 nm scale fabrication of metal oxide semiconductor field effect transistor (MOSFET) devices, led to development of three dimensional multi-gate such as fin field effect transistors (FinFET) and tri-gate devices. FinFET and tri-gate devices enhance gate control, suppress current leakages, and reduce short-channel effects, when compared to conventional single-gate silicon (Si) or silicon on insulator (SOI) MOSFETs with a dual gate SOI arrangement, by suppressing short-channel effects and drain induced barrier lowering (DIBL) effects, which has a lower junction capacitance and may implement a light-doping of the channel. A threshold voltage may be adjusted by setting a work function of the metal gate so that a driving current which is about two times larger may be obtained, and decrease requirements for an equivalent oxide thickness (EOT). As compared with a dual-gate device, in a tri-gate device, the gate surrounds a top surface and two side surfaces of the channel region, and the ability of gate control is further enhanced.
Further advantages may be possible with gate-all-around nanowires multi-gate devices with better gate control more effective suppression of short channel effects, and advantages in the scale-down process for a sub 14 nm technique. However, sufficient driving current can't be provided in an equivalent silicon area due to smaller conductive channels.
For example, for a device with an equivalent line width of about 1 μm, the dimensions of the gate-all-around nanowires device need to meet the following requirements: d*n+(n−1)*s=1 μm and π*d*n>1 μm, in which d is a diameter of a single nanowire, n is the number of nanowires, and s is the interval (spacing) between the nanowires. Thus, for diameters of about 3, 5, 7 and 10 nm, the intervals between the nanowires have to be smaller than 6.4 nm, 10.6 nm, 15 nm and 21.4 nm, respectively. To obtain a gate width which is equivalent to that of bulk silicon of about 1 μm, the parallel arrangements of the nanowires device should be more compact. Based on the current exposure and etching technique for FinFET (the intervals between the fins is about 60 nm), it is difficult to manufacture a stereo arrangements for such a nanowires with tiny intervals.
One way to increase the driving current of a transistor is to implement a stack of gate-all-around nanowires arrangement along a vertical direction. However, attempts to implement a stack of gate-all-around nanowires have not been compatible with conventional manufacturing processes, and have been costly. For example, an existing approach for making stacked nanowires is to grow alternating layers of Si and SiGe, by a method of heterochronous epitaxial growth on a buried oxide (BOX) layer, and selectively remove SiGe by a method such as wet etching so as to leave a stack of Si nanowires. Such a method is seriously limited by the quality of epitaxial grown thin layers and greatly increases the cost.
Therefore, there is a need for nanowires MOS transistor devices, and methods to manufacture nanowires MOS transistors for which the equivalent width of the conductive channel is increased, and the driving current is enhanced.